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Freescale Semiconductor Advance Information
Document Number: MC33927 Rev. 2.0, 8/2007
Three-Phase Field Effect Transistor Pre-Driver
The 33927 is a Field Effect Transistor (FET) pre-driver designed for three-phase motor control and similar applications. The integrated circuit (IC) uses SMARTMOSTM technology. The IC contains three high-side FET pre-drivers and three low-side FET pre-drivers.Three external bootstrap capacitors provide gate charge to the high side FETs. The IC interfaces to a MCU via six direct input control signals, a SPI port for device setup and asynchronous reset, enable and interrupt signals. Both 5.0V and 3.0V logic level inputs are accepted and 5.0V logic level outputs are provided. Features * Fully specified from 8.0V to 40V covers 12V and 24V automotive systems * Extended operating range from 6.0V to 58V covers 12V and 42V systems * 1.0A gate drive capability with protection * Protection against reverse charge injection from CGD and CGS of external FETs * Includes a charge pump to support full FET drive at low battery voltages * Deadtime is programmable via the SPI port * Simultaneous output capability enabled via safe SPI command * Pb-Free Packaging Designated by Suffix Code EK
VBAT
33927
FET PRE-DRIVER
EK SUFFIX (Pb-FREE) 98ASA99334D 54-PIN SOICW-EP
ORDERING INFORMATION
Device MCZ33927EK/R2 Temperature Range (TA) -40C to 125C Package 54 SOICW-EP
33927
VPUMP PUMP VPWR VLS VDD VSS
3 3 3
VBAT PA_HS_G PB_HS_G PC_HS_G
PA_HS_S PB_HS_S PC_HS_S
MCU OR DSP
PX_HS PX_LS PHASEX CS SI SCLK SO RST INT EN1 EN2 GND
PA_LS_G PB_LS_G PC_LS_G PGND_X AMP_P AMP_N AMP_OUT
RSEN
Figure 1. 33927 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
PUMP
VPWR
VBAT
VPUMP PGND
MAIN CHARGE PUMP TRICKLE CHARGE PUMP 5V REG. VDD OSCILLATOR VLS REG. HOLD -OFF CIRCUIT
VLS VDD UV DETECT
3X
RST INT EN1 EN2 PX_HS PX_LS CS SI SCLK SO
3 3 3
T-LIM VBAT + DESAT. 1.4V COMP + HIGHSIDE DRIVER
PX_BOOT
PX_HS_G
CONTROL LOGIC
PX_HS_S + PHASE VBAT COMP. LOWSIDE DRIVER + I-SENSE AMP. AMP_N AMP_P VLS_CAP PGNDX PX_LS_G
PHASEX OC_OUT GND(2) + OVER-CUR. COMP.
VSS OC_TH AMP_OUT
Figure 2. 33927 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
PHASEA PGND EN1 EN2 RST N/C PUMP VPUMP VBAT PHASEB PHASEC PA_HS PA_LS VDD PB_HS PB_LS INT CS SI SCLK SO PC_LS PC_HS AMP_OUT AMP_N AMP_P OC_OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 .35 34 33 32 31 30 29 28
VPWR N/C N/C VLS N/C N/C PA_BOOT PA_HS_G PA_HS_S PA_LS_G PGNDA PB_BOOT PB_HS_G PB_HS_S PB_LS_G PGNDB PC_BOOT PC_HS_G PC_HS_S PC_LS_G PGNDC N/C VLS_CAP GND1 GND0 VSS OC_TH
Figure 3. 33927 Pin Connections Table 1. 33927 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin 1 2 3 4 5 6, 33, 49, 50, 52, 53 7 8 9 10 11 Pin Name PHASEA PGND EN1 EN2 RST N/C PUMP VPUMP VBAT PHASEB PHASEC Pin Function Digital Output Ground Digital Input Digital Input Digital Input - Power Drive Out Power Input Digital Input Digital Output Digital Output Formal Name Phase A Power Ground Enable 1 Enable 2 Reset No Connect Pump Voltage Pump Voltage Battery Phase B Phase C Definition Totem Pole output of Phase A comparator. This output is low when the voltage on PA_HS_S (Source of High-Side FET) is less than 50% of VBAT Power ground for charge pump Logic signal input must be high (ANDed with EN2) to enable any gate drive output. Logic signal input must be high (ANDed with EN1) to enable any gate drive output Reset input These pins do not connect Charge pump output Charge pump supply Battery supply Totem Pole output of Phase B comparator. This output is low when the voltage on PB_HS_S (Source of High-Side FET) is less than 50% of VBAT Totem Pole output of Phase C comparator. This output is low when the voltage on PC_HS_S (Source of High-Side FET) is less than 50% of VBAT
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PIN CONNECTIONS
Table 1. 33927 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30, 31 32 34 35 36 37 38 39 40 41 42 43 44 45 Pin Name PA_HS PA_LS VDD PB_HS PB_LS INT CS SI SCLK SO PC_LS PC_HS AMP_OUT AMP_N AMP_P OC_OUT OC_TH VSS GND VLS_CAP PGNDC PC_LS_G PC_HS_S PC_HS_G PC_BOOT PGNDB PB_LS_G PB_HS_S PB_HS_G PB_BOOT PGNDA PA_LS_G Pin Function Digital Input Digital Input Analog Output Digital Input Digital Input Digital Output Digital Input Digital Input Digital Input Digital Output Digital Input Digital Input Analog Output Analog Input Analog Input Digital Output Formal Name Phase A High-Side Phase A Low-Side VDD Regulator Phase B High-Side Phase B Low-Side Interrupt Chip Select Serial In Serial Clock Serial Out Phase C Low-Side Phase C High-Side Amplifier Output Amplifier Invert Amplifier Non-Invert Overcurrent Out Definition Active low input logic signal enables the High-Side Driver for Phase A Active high input logic signal enables the Low-Side Driver for Phase A VDD regulator output. Internally generated 5V supply Active low input logic signal enables the High-Side Driver for Phase B Active high input logic signal enables the Low-Side Driver for Phase B Interrupt pin output Chip Select input. It frames SPI commands and enables SPI port Input data for SPI port. Clocked on the falling edge of SCLK, MSB first Clock for SPI port and typically is 3.0 MHz Output data for SPI port. Tri-state until CS becomes low Active high input logic signal enables the Low-Side Driver for Phase C Active low input logic signal enables the High-Side Driver for Phase C Output of the current-sensing amplifier Inverting input of the current-sensing amplifier Non-inverting input of the current-sensing amplifier Totem pole digital output of the Over-current Comparator
Analog Input Overcurrent Threshold Threshold of the overcurrent detector Ground Ground Voltage Source Supply Ground reference for logic interface and power supplies Ground Substrate and ESD reference, connect to VSS VLS Regulator connection for additional output capacitor, providing low impedance supply source for Low-Side Gate Drive Gate current return for the Low-Side FETs for Phase C gate current
Analog Output VLS Regulator Output Capacitor Power Input Phase C Return
Power Output Phase C Low-Side Gate Gate drive output for Phase C Low-Side Drive Power Input Power Output Analog Input Power Input Phase C High-Side Source Phase C High-Side Gate Drive Phase C Bootstrap Phase B Return Source connection for Phase C High-Side FET Gate Drive for output Phase C High-Side FET Bootstrap capacitor for Phase C Gate current return for the Low-Side FETs for Phase B
Power Output Phase B Low-Side Gate Gate Drive for output Phase B Low-Side Drive Power Input Power Output Analog Input Power Input Phase B High-side Source Phase B High-Side Gate Drive Phase B Bootstrap Phase A Return Source connection for Phase B High-Side FET Gate Drive for output Phase B High-Side Bootstrap capacitor for Phase B Gate current return for the Low-Side FETs for Phase A
Power Output Phase A Low-Side Gate Gate Drive for output Phase A Low-Side Drive
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
Table 1. 33927 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin 46 47 48 51 54 Pin Name PA_HS_S PA_HS_G PA_BOOT VLS VPWR EP Pin Function Power Input Power Output Analog Input Analog Output Power Input Ground Formal Name Phase A High-Side Source Phase A High-Side Gate Drive Phase A Bootstrap VLS Regulator Voltage Power Exposed Pad Definition Source connection for Phase A High-Side FET Gate Drive for output Phase A High-Side Bootstrap capacitor for Phase A VLS regulator output. Power supply for the gate drives Power supply input for gate drives Device will perform as specified with the Exposed Pad un-terminated (floating) however, it is recommended that the Exposed Pad be terminated to pin 29 (VSS) and system ground
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS VBAT Supply Voltage Normal Operation (Steady-State) Transient Survival(1) VPWR Supply Voltage Normal Operation (Steady-State) Transient Survival(1) Charge Pump (PUMP, VPUMP) VLS Regulator Outputs (VLS, VLS_CAP) Logic Supply Voltage Logic Output (INT, SO, PHASEA, PHASEB, PHASEC, OC_OUT)(2) Logic Input Pin Voltage (EN1, EN2, Px_HS, Px_LS, SI, SCLK, CS, RST) 10mA Amplifier Input Voltage (Both Inputs-GND), (AMP_P - GND) or (AMP_N - GND) 6mA source or sink Over-current comparator threshold 10mA Driver Output Voltage
(3)
Symbol
Value
Unit
VBAT 58 -1.5 to 80 VPWR 58 -1.5 to 80 VPUMP VLS VDD VOUT VIN VIN_A -7.0 to 10.0 VOC VBOOT VHS_G VLS_G -0.3 to 7.0 75 75 16 -0.3 to 40 -0.3 to 18 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0
V
V
V V V V V V
V V
High-Side bootstrap (PA_BOOT, PB_BOOT, PC_BOOT) High-Side (PA_HS_G, PB_HS_G, PC_HS_G) Low-Side (PA_LS_G, PB_LS_G, PC_LS_G) Driver Voltage Transient Survival High-Side (PA_HS_G, PB_HS_G, PC_HS_G, PA_HS_S, PB_HS_S, PC_HS_S) Low-Side (PA_LS_G, PB_LS_G, PC_LS_G, PGNDA, PGNDB, PGNDC)
V VHS_G VHS_S VLS_G VPGND -7.0 -7.0 -7.0 -7.0 -0.1 to 0.1 A V 2000 1000 750
Continuous Output Current ESD Voltage
(4)
IGATE VESD
Human Body Model - HBM (All pins except for the pins listed below) Pins: PA_Boot, PA_HS_S, PA_HS_G, PB_Boot, PB_HS_S, PB_HS_G, PC_Boot, PC_HS_S, PC_HS_G, VPWR Charge Device Model - CDM Notes 1. 2. 3. 4.
The device will withstand load dump transient as defined by ISO7637 with peak voltage of 80V. Short-circuit proof, the device will not be damaged or induce unexpected behavior due to shorts to external sources within this range. This voltage should not be applied without also taking voltage at HS_S and voltage at PGND_x into account. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100pF, RZAP = 1500) and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF).
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings THERMAL RATINGS Storage Temperature Operating Junction Temperature Thermal Resistance
(5)
Symbol
Value
Unit
TSTG TJ
-55 to +150 -40 to +150
C C C/W
Junction-to-Case Soldering Temperature(6)
RJC TSOLDER
3.0 Note 7 C
Notes 5. Case is considered EP - pin 55 under the body of the device. The actual power dissipation of the device is dependent on the operating mode, the heat transfer characteristics of the board and layout and the operating voltage. See Figure 19 and Figure 20 for examples of power dissipation profiles of two common configurations. Operation above the maximum operating junction temperature will result in a reduction in reliability leading to malfunction or permanent damage to the device. 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 8.0V VPWR = VBAT 40V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER INPUTS VBAT Supply Voltage Startup Threshold(8) VBAT Supply Current, VPWR = VBAT = 40V RST and ENABLE = 5.0V No output loads on Gate Drive Pins, No PWM No output loads on Gate Drive Pins, 20kHz, 50% Duty Cycle VPWR Supply Current, VPWR = VBAT = 40V RST and ENABLE = 5.0V No output loads on Gate Drive Pins, No PWM Output Loads = 620nC per FET, 20kHz PWM(9) Sleep State Supply Current, RST = 0V VBAT = 40V VPWR = 40V Sleep State Output Gate Voltage IG < 100A Trickle Charge Pump (Bootstrap Voltage) VBAT = 14V Bootstrap Diode Forward Voltage at 10mA VDD V INTERNAL REGULATOR VDD Output Voltage, VPWR = 8V to 40V, C = 0.47F(10) External Load IDD_EXT = 0 to 1.0mA Internal VDD Supply Current, VDD = 5.5V, No External Load VLS REGULATOR Peak Output Current, VPWR = 16V, VLS = 10V Linear Regulator Output Voltage, IVLS = 0 to VLS Disable Threshold(12) 60mA(11) IPEAK VLS VTHVLS 350 13.5 7.5 600 15 8.0 800 17 8.5 mA V V IDD - - 12 mA VDD 4.5 - 5.5 V VF - - 1.2 V VBoot 22 28 32 V IBAT IPWR VGATESS - - - 14 56 - 30 100 1.3 V - - 11 - 20 95 A IPWR_ON - - 1.0 - - 10 mA VBAT_ST IBAT - 6.0 8.0 V mA Symbol Min Typ Max Unit
Notes 8. When minimum system voltage could be less than 14V operation with the Charge Pump is recommended. VBAT must exceed this threshold in order for the Charge Pump and VDD regulator to startup and drive VPWR to > 8.0V. Once VPWR exceeds 8.0V, the circuits will continue to operate even if VBAT drops below 6.0V. 9. 10. 11. 12. This parameter is guaranteed by design. It is not production tested. Minimum external capacitor for stable VDD operation is 0.47F. Recommended external capacitor for the VLS regulator is 2.2F low ESR at each pin VLS and VLS_CAP. When VLS is less than this value, the outputs are disabled and HOLDOFF circuits are active.
33927
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 8.0V VPWR = VBAT 40V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic CHARGE PUMP Charge Pump High-Side Switch On-Resistance Low-Side Switch On-Resistance Regulation Threshold Difference(13)(15) Charge Pump Output Voltage(14), (15) IOUT = 40mA, 6.0V < VBAT < 8.0V IOUT = 40mA, VBAT > = 8.0V GATE DRIVE High-Side Driver On-Resistance (Sourcing) VPWR = VBAT = 16V, -40C TA 25C VPWR = VBAT = 16V, 25C < TA 125C High-Side Driver On-Resistance (Sinking) VPWR = VBAT = 16V High-Side Current Injection Allowed Without Malfunction(15), (16) Low-Side Driver On-Resistance (Sourcing) VPWR = VBAT = 16V, -40C TA 25C VPWR = VBAT = 16V, 25C < TA 125C Low-Side Driver On-Resistance (Sinking) VPWR = VBAT = 16 V Low-Side Current Injection Allowed Without Malfunction(15), (16) Gate Source Voltage, VPWR = VBAT = 40V High-Side, IGATE = 0 Low-Side, IGATE = 0 High-Side Gate Drive Output Leakage Current, Per Output(18)
(17)
Symbol
Min
Typ
Max
Unit
RDS(on)_HS RDS(on)_LS VTHREG VCP
- - 250
6.0 5.0 500
10 9.4 900

mV V
8.5 12
9.5 -
- -
RDS(on)_H_SRC - - RDS(on)_H_SINK - IHS_INJ RDS(on)_L_SRC - - RDS(on)_L_SINK ILS_INJ VGS_H VGS_L IHS_LEAK - - - - 6.0 8.5 3.0 - - - 3.0 0.5 - - 6.0 8.5
A
V
- 13 13 -
- 14.8 15.4 -
0.5 16.5 17 18
A
Notes 13. When VLS is this amount below the normal VLS linear regulation threshold, the pump is enabled. 14. With recommended external components (1.0F, MUR 120 diode). The Charge Pump is designed to supply the gate currents of a system with 100A FETs in a 12V application. 15. This parameter is a design characteristic, not production tested. 16. Current injection only occurs during output switch transitions. The IC is immune to specified injected currents for a duration of approximately 1 s after an output switch transition. 1 s is sufficient for all intended applications of this IC. 17. If a slightly higher gate voltage is required, larger bootstrap capacitors are required. At high duty cycles, the bootstrap voltage may not recover completely, leading to a higher output on-resistance. This effect can be minimized by using low ESR capacitors for the bootstrap and the VLS capacitors. 18. A small internal charge pump will supply up to 30 A nominal to compensate for leakage on the high-side FET gate output and maintain voltages after bootstrap events. It is not intended for external components to be connected to the High-Side FET gate, but small amounts of additional leakage can be accommodated.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 8.0V VPWR = VBAT 40V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic OVERCURRENT COMPARATOR Common Mode Input Range Input Offset Voltage Overcurrent Comparator Threshold Hysteresis(19) Output Voltage High-Level at IOH = -500A Low-Level at IOL = 500A HOLD OFF CIRCUIT VDD Threshold (VDD Falling) RST pin High Hold Off Current (At Each GATE Pin) 3.0V < VBAT < 40V(20) IHOLD 10 - 300 A VDD_TH 1.5 - 4.0 V VOH VOL 0.85 VDD - - - VDD 0.5 VCM VOS_OC VOC_HYST 2.0 -50 50 - - VDD-0.02 50 300 V mV mV V Symbol Min Typ Max Unit
PHASE COMPARATOR High-Level Input Voltage Threshold Low-Level Input Voltage Threshold High-Level Output Voltage at IOH = -500A Low-Level Output Voltage at IOL = 500A High-Side Source Input Resistance(19), (23) DESATURATION DETECTOR Desaturation Detector Threshold(21) CURRENT SENSE AMPLIFIER Recommended External Series Resistor (See Figure 9) Recommended External Feedback Resistor (See Figure 9) Limited by the Output Voltage Dynamic Range Maximum Input Differential Voltage (See Figure 9) VID = VAMP_P - VAMP_N Input Common Mode Range(19), (22) Input Offset Voltage RS = 1k, VCM = 0.0V Input Offset Voltage Drift(19) Input Bias Current VCM = 2.0V Notes 19. This parameter is a design characteristic, not production tested. 20. The hold off circuit is designed to operate over the full operating range of VBAT. The specification indicates the conditions used in production test. 21. Desaturation is measured as the voltage drop below VBAT, thus the threshold is compared to the drain-source voltage of the external high-side FET. See Figure 5. 22. As long as one input is within VCM the output is guaranteed to have the correct phase. Exceeding the common mode rails will not cause a phase inversion on the output. 23. Input resistance is impedance from high-side source and is referenced to ground. Approximate tolerance is 20%. VOS/T Ib - -200 -10 - - +200 V/C nA VC VOS 0 -15 - - 3.0 +15 V mV VID -800 - +800 mV RS RFB - 5.0 1.0 - - 15 k k VDES_TH 1.2 1.4 1.6 V VIH_TH VIL_TH VOH VOL RIN 0.5 VBAT 0.3 VBAT 0.85 VDD - - - - - - 50 0.65 VBAT 0.45 VBAT VDD 0.5 - V V V V k
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 8.0V VPWR = VBAT 40V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic CURRENT SENSE AMPLIFIER (CONTINUED) Input Offset Current IOS = IAMP_P - IAMP_N Input Offset Current Drift (24) Output Voltage High-Level with RLOAD = 10 k to VSS Low-Level with RLOAD = 10 k to VDD Differential Input Resistance Output Short Circuit Current Common-Mode Input Capacitance at 10 kHz Common-Mode Rejection Ratio at DC CMRR = 20*Log ((VOUT_diff/VIN_diff) * (VIN_CM/VOUT_CM)) Large Signal Open Loop Voltage Gain (DC) (24)(25) Gain Margin at Gain = 5.0 (24)(25) Nonlinearity (24)(25) RL = 1k, CL = 500pF, 0.3 < VO < 4.8V, Gain = 5.0 to 15 Notes 24. This parameter is a design characteristic, not production tested. 25. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors. AOL AM NL - - -1.0 60 5.0 - - - +1.0 dB dB %
(24)(25)
Symbol
Min
Typ
Max
Unit
IOS IOS/T VOH VOL RI ISC CI CMRR
-80
-
+80
nA
- VDD-0.2 - 1.0 5.0 - 60
40 - - - - - 80
- VDD 0.2 - - 10 -
pA/C V
M mA pF dB
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 8.0V VPWR = VBAT 40V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic SUPERVISORY AND CONTROL CIRCUITS Logic Inputs (Px_LS, Px_HS, EN1, EN2) (27) High-Level Input Voltage Threshold Low-Level Input Voltage Threshold Logic Inputs (SI, SCLK, CS)
(26) (27)
Symbol
Min
Typ
Max
Unit
V VIH VIL VIH VIL VIHYS IINPD - 0.9 - 0.9 100 8.0 - - - - 250 - 2.1 - V 2.1 - 450 18 mV A
,
High-Level Input Voltage Threshold Low-Level Input Voltage Threshold Input Logic Threshold Hysteresis
(26)
Inputs Px_LS, SI, SCLK, CS, Px_HS, EN1, EN2 Input Pull-Down Current, (Px_LS, SI, SCLK, EN1, EN2) 0.3 VDD VIN VDD Input Pull-Up Current, (CS, Px_HS) (28) 0 VIN 0.7 VDD Input Capacitance
(26)
IINPU 10 CIN VTH_RST RRST - - 15 25 - A pF
0.0 VIN 5.5V RST Threshold (29) RST Pull-Down Resistance 0.3 VDD VIN VDD Power-ON RST Threshold, (VDD Falling) SO High-Level Output Voltage IOH = 1.0mA SO Low-Level Output Voltage IOL = 1.0mA SO Tri-State Leakage Current CS = 0.7 VDD, 0.3 VDD = VSO = 0.7 VDD SO Tri-State Capacitance (26), (30) 0.0 VIN 5.5V INT High-Level Output Voltage IOH = -500A INT Low-Level Output Voltage IOL = 500A THERMAL WARNING Thermal Warning Temperature (26), (31) Thermal Hysteresis (26) Notes 26. This parameter is guaranteed by design, not production tested. 27. Logic threshold voltages derived relative to a 3.3V 10% system. 28. Pull-Up circuits will not allow back biasing of VDD. 29. 30. 31. There are two elements in the RST circuit: 1) one generally lower threshold enables the internal regulator; 2) the second removes the reset from the internal logic. This parameter applies to the OFF state (tri-stated) condition of SO is guaranteed by design but is not production tested. The Thermal Warning circuit does not force IC shutdown above this temperature. It is possible to set a bit in the MASK register to generate an interrupt when overtemperature is detected, and the status bits will always read back the state of the three individual Thermal Warning circuits in the IC. TWARN THYST 150 8 170 10 185 12 C C VOL - - 0.5 V VOH 0.85 VDD - VDD % VDD CSO_T ISO_LEAK_T -1.0 - - 15 1.0 - pF A VSOL - - 0.1 VDD V VTHRST VSOH 3.4 0.9 VDD 4.0 - 4.5 - V V 1.0 40 - 60 2.1 85 V k
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 8.0V VPWR = VBAT 40V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic INTERNAL REGULATORS VDD Power-Up Time (Until INT High) 8.0V VPWR (32) VLS Power-Up Time 16V VPWR (33) CHARGE PUMP Charge Pump Oscillator Frequency Charge Pump Slew GATE DRIVE High-Side Turn-On Time Transition Time from 1.0 to 10V, Load: C = 500pF, Rg = 0, (Figure 7) High-Side Turn-On Delay(35) Delay from Command to 1.0V, (Figure 7) High-Side Turn-Off Time Transition Time from 10 to 1.0V, Load: C = 500pF, Rg = 0, (Figure 8) High-Side Turn-Off Delay(35) Delay from Command to 10V, (Figure 8) Low-Side Turn-On Time Transition Time from 1.0 to 10V, Load: C = 500pF, Rg = 0, (Figure 7) Low-Side Turn-On Delay(35) Delay from Command to 1.0V, (Figure 7) Low-Side Turn-Off Time Transition Time from 10 to 1.0V, Load: C = 500pF, Rg = 0, (Figure 8) Low-Side Turn-Off Delay(35) Delay from Command to 10V, (Figure 8) Same Phase Command Delay Match(36) Thermal Filter Duration (37) tD_DIFF tDUR tD_OFFL 130 -20 8.0 265 0 - 386 +20 30 ns s tOFFL - 20 35 ns tD_ONL 130 265 386 ns tONL - 20 35 ns tD_OFFH 130 265 386 ns tOFFH - 20 35 ns tD_ONH 130 265 386 ns tONH - 20 35 ns ns Rate(34) FOSC SRCP 90 - 125 100 190 - kHz V/s tPU_VDD - - 2.0 tPU_VDD - - 2.0 ms ms Symbol Min Typ Max Unit
Notes 32. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on VDD. 33. 34. 35. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on VLS. This delay includes the expected time for VDD to rise. The charge pump operating at 12V Vbat, 1F pump capacitor, MUR120 diodes and 47F filter capacitor. These delays include all logic delays except deadtime. All internal logic is synchronous with the internal clock. The total delay includes one clock period for state machine decision block, an additional clock period for FULLON mux logic, input synchronization time and output driver propagation delay. Subtract one clock period for operation in FULLON mode which bypasses the state machine decision block. Synchronization time accounts for up to one clock period of variation. See Figure 6. This is the maximum separation or overlap of the High and Low side gate drives due to propagation delays when commanding one ON and the other OFF simultaneously. The output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt.
36. 37.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 8.0V VPWR = VBAT 40V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic GATE DRIVE (CONTINUED) Duty Cycle (38), (39) 100% Duty Cycle Duration
(38) (39)
Symbol
Min
Typ
Max
Unit
tDC , tDC
(40)
0.0 - 10.2
- - 15
96 Unlimited 19.6
% s s
Maximum Programmable Deadtime OVERCURRENT COMPARATOR Overcurrent Protection Filter Time Rise Time (OC_OUT) 10% - 90% CL = 100 pF Fall Time (OC_OUT) 90% - 10% CL = 100 pF PHASE COMPARATOR
tMAX
tOC tROC
0.9 10
- -
3.5 240
s ns
tFOC
10
-
200
ns
Propagation Delay Time to 50% of VDD; CL 100 pF Rising Edge Delay Falling Edge Delay Match Conversion Time (Prop Delay Mismatch of Three Phases) CL = 100 pF
(38)
ns tR tF tMATCH - - - - - - 200 350 100 ns
DESATURATION DETECTOR Desaturation and Phase Error Blanking Time Filter Time
(38)
tBLANK tFILT
4.0
-
8.1
s ns
Fault Must be Present for This Time to Trigger CURRENT SENSE AMPLIFIER Output Settle Time to 99% (38), (41) RL = 1k, CL = 500pF 0.3 < VO < 4.8V Gain = 5 to 15 tSETTLE
560
1000
1230
-
1.0
2.0
s
Notes 38. This parameter is guaranteed by design, not production tested. 39. Maximum duty cycle is actually 100% because there is an internal charge pump to maintain the gate voltage in the 100% on condition. However, in high duty cycle cases, there may not be sufficient time to recharge the bootstrap capacitors during the off time. Large bootstrap capacitors will allow high duty cycles to be obtained for a short time. For applications needing closer to 100% duty cycle, external diodes may optionally be used to provide high peak current charging capability to the bootstrap capacitors. These diodes would be connected between VLS and the Px_BOOTSTRAP pins. In applications with lower gate charge requirements, the maximum duty cycle can also be increased. 40. A Minimum Deadtime of 0.0 can be set via a SPI command. When Deadtime is set via a DEADTIME command, a minimum of 1 clock cycle duration and a maximum of 255 clock cycles is set using the internal time base clock as a reference. Commands exceeding this value limits at this value. 41. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 8.0V VPWR = VBAT 40V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic CURRENT SENSE AMPLIFIER (CONTINUED) Output Rise Time to 90% (43) RL = 1k, CL = 500 pF 0.3 < VO < 4.8V Gain = 5 to 15 Output Fall Time to 10% (43) RL = 1k CL = 500pF 0.3 < VO < 4.8V Gain = 5 to 15 Slew Rate at Gain = 5.0(42) RL = 1 , CL = 20pF Phase Margin at Gain = 5.0(42) Unity Gain Bandwidth
(42)
Symbol
Min
Typ
Max
Unit
tIS_RISE - - 1.0
s
tIS_FALL - - 1.0
s
SR(5)
5.0
-
-
V/s
fM GBW
- -
30 20
- -
MHz
RL = 1 , CL = 100pF Bandwidth at Gain = 15 (42) RL = 1 , CL = 50pF Common Mode Rejection (CMR) (42) with VIN VIN_CM = 400mV*sin(2**freq*t) VIN_DIF = 0.0V, RS = 1k RFB = 15 k, VREFIN = 0.0V CMR = 20*Log(VOUT/VIN_CM) Freq = 100kHz Freq = 1.0MHz Freq = 10MHz SUPERVISORY AND CONTROL CIRCUITS EN1 and EN2 Propagation Delay INT Rise Time CL = 100 pF INT Fall Time CL = 100 pF INT Propagation Time tPROP tRINT tFINT tPROPINT - 10 10 - - - - - 280 250 200 250 ns ns ns ns 50 40 30 - - - - - - CMR dB BWG 2.0 - - MHz
Notes 42. This parameter is guaranteed by design, not production tested. 43. Rise and fall times are measured from the transition of a step function on the input to 90% of the change in output voltage.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 8.0V VPWR = VBAT 40V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic SPI INTERFACE TIMING Maximum Frequency of SPI Operation Internal Time Base Internal Time Base drift from value at 25C
(44) (44) (44)
Symbol
Min
Typ
Max
Unit
fOP fTB TCTB tLEAD tLAG tSISU tSIHOLD tRSI tFSI
(44), (46) (44) (47)
- 13 -5 100 100 25 25 - - - - - 200 17 - - - - - 5.0 5.0 55 100 55 -
5.0 25 5 - - - - - - 100 125 100 -
MHz MHz % ns ns ns ns ns ns ns ns ns ns
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) SI to Falling Edge of SCLK (Required Setup Time) Falling Edge of SCLK to SI (Required Setup Time) SI, CS, SCLK Signal Rise Time SI, CS, SCLK Signal Fall Time
(44) (45) (44) (44)
,
(44) (45)
,
Time from Falling Edge of CS to SO Low Impedance Time from Rising Edge of CS to SO High Impedance Time from Rising Edge of SCLK to SO Data Valid
tSOEN tSODIS tVALID
,
(44) (48)
,
Time from Rising Edge of CS to Falling Edge of the next CS Notes 44. 45. 46. 47. 48.
(44)
tDT
This parameter is guaranteed by design, not production tested. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for valid output status data to be available on SO pin. Time required for output states data to be terminated at SO pin. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
CS
0.2 VDD
tL EA D
ttLA G LAG
SCLK
0 .7 VD D 0 .2 VD D
tDI(SU) tSIHOLD tSISU tDI(HO LD)
SI
0 .7 VD D 0 .2 VD D
MSB in
tSOEN tDO(E N)
tV A LI D
0 .7 VD D 0 .2 VD D
tSODIS tDO (DIS )
SO
MSB out
LSB out
Figure 4. SPI Interface Timing
PX_HS PX_LS FROM DELAY TIMER
DESATURATION FAULT
Figure 5. Desaturation Blanking and Filtering Detail
B PX_HS D CLK DEADTIME CONTROL Q STATE MACHINE MUX D CLK Q A OUT D CLK Q PX_HS_G
PX_HS_S
PX_LS
D CLK
Q
1ST PULSE
D CLK Q A OUT MUX B
D CLK
Q PX_LS_G
EN1 EN2 RST
Figure 6. Deadtime Control Delays
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
50% Px_HS
10V tD_ONH 1 .0 V tONH
Px_HS _G
50% Px_LS
10V tD_ONL 1.0V tONL
Px_LS_G
Figure 7. Driver Turn-On Time and Turn-On Delay
50% Px_HS
10V
Px_HS_G
tD_OFFH
1 .0 V tOFFH
50% Px_ LS 1 0V tD_OFFL 1.0V tOFFL
Px_LS_G
Figure 8. Driver Turn-Off Time and Turn-Off Delay
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
RE F To P rotection Circuits R FB P AMP_P + V ID AMP_N OC_TH AMP_O UT R FBN Rs + V IN Rs R sens e
Figure 9. Current Amplifier and Input Waveform (VIN Voltage Across RSENSE)
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FUNCTIONAL DESCRIPTIONS INTRODUCTION
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
The 33927 provides an interface between an MCU and the large FETs used to drive three-phase loads. A typical load FET may have an on-resistance of 4.0m or less and could require a gate charge of over 400 nC to fully turn on. The IC can operate in automotive 12V to 42V environments. Because there are so many methods of controlling threephase systems, the IC enforces few constraints on driving the FETs. It does provide deadtime (cross-over) blanking and logic, both of which can be overridden, ensuring both FETs in a phase are not simultaneously enabled. A SPI port is used to configure the IC modes.
FUNCTIONAL PIN DESCRIPTION PHASE A (PHASEA)
This pin is the totem pole output of the Phase A comparator. This output is low when the voltage on Phase A high-side source (source of the High-Side load FET) is less than 50 percent of VBAT.
CHARGE PUMP INPUT (VPUMP)
This pin is the input supply for the charge pump circuit. When the charge pump is required, this pin should be connected to a polarity protected supply. Typical applications would connect it to VBAT. This input should never be connected to a supply greater than 40V. If the charge pump is not required this pin may be left floating.
POWER GROUND (PGND)
This pin is power ground for the charge pump. It should be connected to VSS, however routing to a single point ground on the PCB may help to isolate charge pump noise. NOTE: This is NOT the same as the Phase Grounds for each of the Phases.
VBAT INPUT (VBAT)
This pin should be connected to the system battery voltage. It is used to provide power to the internal steady state trickle charge pump and to energize the hold-off circuit. It is also the reference bias for the Phase Comparators and Desaturation Comparator.
ENABLE 1 AND ENABLE 2 (EN1, EN2)
Both of these logic signal inputs must be high to enable any gate drive output. When either or both are low, the internal logic (SPI port, etc.) still functions normally, but all gate drives are forced off (external power FET gates pulled low). The signal is asynchronous. When EN1 and EN2 return high to enable the outputs, each LS driver must be pulsed on before the corresponding HS driver can be commanded on. This ensures that the bootstrap capacitors are charged.
PHASE B (PHASEB)
This pin is the totem pole output of the Phase B comparator. This output is low when the voltage on Phase B high-side source (source of the High-Side load FET) is less than 50 percent of VBAT.
PHASE C (PHASEC)
This pin is the totem pole output of the Phase C comparator. This output is low when the voltage on Phase C high-side source (source of the High-Side load FET) is less than 50 percent of VBAT.
RESET (RST)
When the reset pin is low the integrated circuit (IC) is in a low power state. In this mode all outputs are disabled, internal bias circuits are turned off, and a small pull down current is applied to the output gate drives. The internal logic will be reset within 77ns of RESET going low. When RST is low, the IC will consume minimal current. This input should not be driven above the VDD voltage.
PHASE A HIGH-SIDE INPUT (PA_HS)
This input logic signal pin enables the High-Side Driver for Phase A. The signal is active low, and is pulled up by an internal current source.
CHARGE PUMP OUT (PUMP)
This pin is the switching node of the charge pump circuit. The output of the internal charge pump support circuit. When the charge pump is used, it is connected to the external pumping capacitor. This pin may be left floating if the charge pump is not required.
PHASE A LOW-SIDE INPUT (PA_LS)
This input logic signal pin enables the Low-Side Driver for Phase A. The signal is active high, and is pulled down by an internal current sink.
VDD VOLTAGE REGULATOR (VDD)
This pin is an internally generated 5V supply. The internal regulator provides continuous power to the IC and is a supply
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTIONS INTRODUCTION
reference for the SPI port. A 0.47F (min) decoupling capacitor must be connected to this pin. This regulator is intended for internal IC use and can supply only a small (1mA) external load current. A power-on-reset (POR) circuit monitors this pin and until the voltage rises above the threshold, the internal logic will be reset; driver outputs will be tri-stated and SPI communication disabled. The VDD regulator can be disabled by asserting the RST signal low. The VDD regulator is powered from the VPWR pin.
PHASE C LOW-SIDE INPUT (PC_LS)
This input logic pin enables the Low-Side Driver for Phase C. This pin is an active high, and is pulled down by an internal current sink.
PHASE C HIGH-SIDE INPUT (PC_HS)
This input logic pin enables the High-Side Driver for Phase C. This signal is active low, and is pulled up by an internal current source.
AMPLIFIER OUTPUT (AMP_OUT)
This pin is the output for the current sensing amplifier. It is also the sense input to the overcurrent comparator.
PHASE B HIGH-SIDE CONTROL INPUT (PB_HS)
This pin is the input logic signal, enabling the High-Side driver for Phase B. The signal is active low, and is pulled up by an internal current source.
AMPLIFIER INVERTING INPUT (AMP_N)
The inverting input to the current sensing amplifier.
PHASE B LOW-SIDE INPUT (PB_LS)
This pin is the input logic signal, enabling the Low-Side driver for Phase B. The signal is active high, and is pulled down by an internal current sink.
AMPLIFIER NON-INVERTING INPUT (AMP_P)
The non-inverting input to the current sensing amplifier.
INTERRUPT (INT)
The Interrupt pin is a totem pole logic output. When a fault is detected, this pin will pull high until it is cleared by executing the Clear Interrupt command via the SPI port. The faults capable of causing an interrupt can be masked via the MASK0 and MASK1 SPI registers to customize the response.
OVERCURRENT COMPARATOR OUTPUT (OC_OUT)
The overcurrent comparator output is a totem pole logic level output. A logic high indicates an overcurrent condition.
OVERCURRENT COMPARATOR THRESHOLD (OC_TH)
This input sets the threshold level of the overcurrent comparator.
CHIP SELECT (CS)
Chip select is a logic input that frames the SPI commands and enables the SPI port. This signal is active low, and is pulled up by an internal current source.
VOLTAGE SOURCE SUPPLY (VSS)
VSS is the ground reference for the logic interface and power supplies.
SERIAL IN (SI)
The Serial In pin is used to input data to the SPI port. Clocked on the falling edge of SCLK, it is the most significant bit (MSB) first. This pin is pulled down by an internal current sink.
GROUND (GND0,GND1)
These two pins are connected internally to VSS by a 1.0 resistor. They provide device substrate connections and also the primary return path for ESD protection.
VLS REGULATOR CAPACITOR (VLS_CAP) SERIAL CLOCK (SCLK)
This logic input is the clock is used for the SPI port. The SCLK typically runs at 3 MHz (up to 5 MHz) and is pulled down by an internal current sink. This connection is for a capacitor which will provide a low impedance for switching currents on the gate drive. A low ESR decoupling capacitor, capable of sourcing the pulsed drive currents must be connected between this pin and VSS. This is the same DC node as VLS, but it is physically placed on the opposite end of the IC to minimize the source impedance to the gate drive circuits.
SERIAL OUT (SO)
Output data for the SPI port streams from this pin. It is tristated until CS is low. New data appears on rising edges of SCLK in preparation for latching by the falling edge of SCLK on the master.
PHASE C GROUND (PGNDC)
The phase C power ground is the pin used to return the gate currents from the low side FET. Best performance is normally realized by connecting this node directly to the source of the low side FET for phase C.
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FUNCTIONAL DESCRIPTIONS INTRODUCTION
PHASE C LOW-SIDE GATE (PC_LS_G)
This is the gate drive for the phase C low side output FET. It provides a high current with a low impedance to turn on and off the low side FET. A low impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FET. This output has been designed to resist the influence of negative currents also.
PHASE B HIGH-SIDE GATE (PB_HS_G)
This is the gate drive for the phase B high side output FET. This pin provides the gate bias to turn the external FET on or off. The gate voltage is limited to about 15V above the FET source voltage. A low impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has been designed to resist the influence of negative currents also.
PHASE C HIGH-SIDE SOURCE (PC_HS_S)
The source connection for the phase C high side output FET is the reference voltage for the gate drive on the high side FET and also the low voltage end of the bootstrap capacitor.
PHASE B BOOTSTRAP (PB_BOOT)
This is the bootstrap capacitor connection for phase B. A capacitor (typically 0.1F) connected between PB_HS_S and this pin provides the gate voltage and current to drive the external FET gate. The voltage across this capacitor is limited to about 15V.
PHASE C HIGH-SIDE GATE (PC_HS_G)
This is the gate drive for the phase C high side output FET. This pin provides the gate bias to turn the external FET on or off. The gate voltage is limited to about 15V above the FET source voltage. A low impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has been designed to resist the influence of negative currents also.
PHASE A GROUND (PGNDA)
The phase A power ground is the pin used to return the gate currents from the low side FET. Best performance is normally realized by connecting this node directly to the source of the low side FET for phase A.
PHASE A LOW-SIDE GATE (PA_LS_G)
This is the gate drive for the phase A low side output FET. It provides a high current with a low impedance to turn on and off the low side FET. A low impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FET. This output has been designed to resist the influence of negative currents also.
PHASE C BOOTSTRAP (PC_BOOT)
This is the bootstrap capacitor connection for phase C. A capacitor (typically 0.1F) connected between PC_HS_S and this pin provides the gate voltage and current to drive the external FET gate. The voltage across this capacitor is limited to about 15V.
PHASE B GROUND (PGNDB)
The phase B power ground is the pin used to return the gate currents from the low side FET. Best performance is normally realized by connecting this node directly to the source of the low side FET for phase B.
PHASE A HIGH-SIDE SOURCE (PA_HS_S)
The source connection for the phase A high side output FET is the reference voltage for the gate drive on the high side FET and also the low voltage end of the bootstrap capacitor.
PHASE B LOW-SIDE GATE (PC_LS_G)
This is the gate drive for the phase B low side output FET. It provides a high current with a low impedance to turn on and off the low side FET. A low impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FET. This output has been designed to resist the influence of negative currents also.
PHASE A HIGH-SIDE GATE (PA_HS_G)
This is the gate drive for the phase A high side output FET. This pin provides the gate bias to turn the external FET on or off. The gate voltage is limited to about 15V above the FET source voltage. A low impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has been designed to resist the influence of negative currents also.
PHASE B HIGH-SIDE SOURCE (PB_HS_S)
The source connection for the phase B high side output FET is the reference voltage for the gate drive on the high side FET and also the low voltage end of the bootstrap capacitor.
PHASE A BOOTSTRAP (PA_BOOT)
This is the bootstrap capacitor connection for phase A. A capacitor (typically 0.1F) connected between PA_HS_S and this pin provides the gate voltage and current to drive the external FET gate. The voltage across this capacitor is limited to about 15V.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTIONS INTRODUCTION
VLS REGULATOR (VLS)
VLS is the gate drive power supply regulated at approximately 15V. This is an internally generated supply from VPWR. It is the source for the low side gate drive voltage, and also the high side bootstrap source. A low ESR decoupling capacitor, capable of sourcing the pulsed drive currents, must be connected between this pin and VSS or PGND.
well as supplying power to the low-side gate drivers and the VDD regulator. An internal regulator regulates the actual gate voltages. This pin can be connected to system battery voltage if power dissipation is not a concern.
EXPOSED PAD (EP)
The primary function of the Exposed Pad is to conduct heat out of the device. This pad may be connected electrically to the substrate of the device.The device will perform as specified with the Exposed Pad un-terminated (floating). However, it is recommended that the Exposed Pad be terminated to pin 29 (VSS) and the system ground.
VPWR INPUT (VPWR)
VPWR is the power supply input for VLS and VDD. Current flowing into this input recharges the bootstrap capacitors as
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL INTERNAL BLOCK DESCRIPTION INTRODUCTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
LOGIC INPUTS AND INTERFACE
BOOTSTRAP SUPPLY
LOW-SIDE DRIVERS
HIGH-SIDE DRIVERS
CHARGE PUMP
Figure 10. Functional Internal Block Description All functions of the IC can be described as the following locked by a SPI command (FULLON, Desaturation Fault, five major functional blocks: Zero-Deadtime). SPI commands can also determine how the various faults are (or are not) reported. * Logic Inputs and Interface * Read back of internal registers. * Bootstrap Supply The status of the 33927 Status Registers can be read back * Low-Side Drivers by the Master (DSP or MCU). * High-Side Drivers The Px_HS and Px_LS logic inputs are edge sensitive. * Charge Pump This means the leading edge on an input will cause the complementary output to immediately turn off and the LOGIC INPUTS AND INTERFACE selected one to turn on after the deadtime delay as illustrated This section contains the SPI port, control logic, and shootin Figure 11. The deadtime delay timer starts when the through timers. corresponding FET was commanded off (see Figure 6 and The IC logic inputs have Schmitt trigger inputs with Figure 11). hysteresis. Logic inputs are 3V compatible. The logic outputs are driven from the internal supply of approximately 5.0V. When the internal supply is not enabled, the SO pin should PA _HS not be externally driven high. The SPI registers and functionality is described completely in the LOGIC COMMANDS AND REGISTERS section of this PA_LS document. SPI functionality includes the following: * Programming of deadtime delay--This delay is De adt ime De lay adjustable in approximately 50 ns steps from 0 ns to PA_HS_G 12 s. Calibration of the delay, because of internal IC variations, is performed via the SPI. * Enabling of simultaneous operation of high-side and PA_LS_G low-side FETs--Normally, both FETs would not be enabled simultaneously. However, for certain applications Figure 11. Edge Sensitive Logic Inputs (Phase A) where the load is connected between the high-side and low-side FETs, this could be advantageous. If this mode is BOOTSTRAP SUPPLY (VPWR) enabled, the blanking time delay will be disabled. A sequence of commands may be required to enable this This is the portion of the IC providing current to recharge function to prevent inadvertent enabling. In addition, this the bootstrap capacitors. It also supplies the peak currents command can only be executed once after reset to enable required for the low-side gate drivers. or disable simultaneous turn-on. The power for the gate drive circuits is provided through * Setting of various operating modes of the IC and the VPWR pin. This pin can be connected to VBAT and is enabling of interrupt sources. capable of withstanding up to the full load dump voltage of the The 33927 allows different operating modes to be set and system. However, the IC only requires a low-voltage supply
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL INTERNAL BLOCK DESCRIPTION INTRODUCTION
on this pin, typically 15V. Higher voltages on the pin increases the IC power dissipation. In 12V systems the supply voltage can fall as low as 6.0V. This limits the gate voltage capable of being applied to the FETs and reduces system performance due to the higher FET on-resistance. To allow a higher gate voltage to be supplied, the IC also incorporates a charge pump. The switches and control circuitry are internal; the capacitors and diodes are external (see Figure 17).
It can be recharged by activating the low-side switches for a brief period, or by attaching external bleed resistors to the HS_S pins to GND. In order to achieve a 100% duty cycle operation of the high-side external FETs, a fully integrated trickle charge pump provides the charge necessary to fully enhance the external FET gates. The slew rate of the external output FET is limited by the driver output impedance, overall (external and internal) gate resistance and the load capacitance. To ensure the low-side FET is not turned on by a large positive dV/dt on the drain of the low side FET, the turn-on slew rate of the high-side should be limited. If the slew rate of the high side is limited by the gate-drain capacitance of the high side FET, then the displacement current injected into the low-side gate drive output will be approximately the same value. Therefore, to ensure the low side drivers can be held off, the voltage drop across the low side gate driver must be lower than the threshold voltage of the low side FET (see Figure 12). Similarly, during large negative dV/dt, the high side FET will be able to remain off if its gate drive low side switch, develops a voltage drop less than the threshold voltage of the high side FET. The gate drive low side switch discharges the gate to the source. Additionally, during negative dV/dt the low side gate drive could be forced below ground. The low side FETs must not inject detrimental substrate currents in this condition. The occurrence of these cases depends on the polarity of the load current during switching.
LOW SIDE DRIVERS
These three drivers turn on and off the external low side FETs. The circuits provide a low impedance drive to the gate, ensuring the FETs remain off in the presence of high dV/dt transients on their drains. Additionally, these output drivers isolate the other portions of the IC from currents capable of being injected into the substrate due to rapid dV/dt transients on the FET drains. Low-side drivers switch power from VLS to the gates of the low-side FETs. The low-side drivers are capable of providing a typical peak current of 2.0A. This gate drive current may be limited by external resistors in order to achieve a good tradeoff between the efficiency and EMC (Electro-Magnetic Compatibility) compliance of the application. the low side driver uses high side PMOS for turn on and low side isolated LDMOS for turn off. The circuit ensures the impedance of the driver remains low, even during periods of reduced current. Current limit is blanked immediately after subsequent input state change in order to ensure device stays off during dV/dt transients.
HIGH SIDE DRIVERS
These three drivers switch the voltage across the bootstrap capacitor to the external high side FETs. The circuits provide a low-impedance drive to the gate, ensuring the FETs remain off in the presence of high dV/dt transients on their sources. Further, these output drivers isolate the other portions of the IC from currents capable of being injected into the substrate due to rapid dV/dt transients on the FETs. The high-side drivers deliver power from their bootstrap capacitor to the gate of the external high-side FET, thus turning the high-side FET on. The high-side driver uses a level shifter, which allows the gate of the external high-side FET to be turned off by switching to the high-side FET source. Because the gate supply voltage for the high-side drivers is obtained from the bootstrap supply, a short time is required after the application of power to the IC to charge the bootstrap capacitors. To ensure this occurrence, the internal control logic will not allow a high-side switch to be turned on after entering the ENABLE state until the corresponding low side switch is enabled at least once. Caution must be exercised after a long period of inactivity of the low-side switches, to verify the bootstrap capacitor is not discharged.
Figure 12. Positive DV/dt Transient
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL INTERNAL BLOCK DESCRIPTION INTRODUCTION
DRIVER FAULT PROTECTION
The 33927 IC integrates several protection mechanisms against various faults. The first of them is the Current Sense Amplifier with the Overcurrent Comparator. These two blocks are common for all three driver phases.
Current Sense Amplifier
This amplifier is usually connected as a differential amplifier (see Figure 9). It senses a current flowing through the external FETs as a voltage across the current sense resistor RSENSE. Since the amplifier common mode range does not extend below ground, it is necessary to use an external reference to permit measuring both positive and negative currents. The amplifier output can be monitored directly (e.g. by the microcontroller's ADC) at the AMP_OUT pin, providing the means for closed loop control with the 33927. The output voltage is internally compared with the Overcurrent Comparator threshold voltage (see Figure 17).
Overcurrent Comparator
The amplified voltage across the Rsense is compared with the pre-set threshold value by the Overcurrent Comparator input. If the Current Sense Amplifier output voltage exceeds the threshold of the Overcurrent Comparator it would change the status of its output (OC_OUT pin) and the fault condition would be latched (see Figure 15). The occurrence of this fault would be signalled by the return value of the Status Register 0. If the proper Interrupt Mask has been set, this fault condition will generate an interrupt - the INT pin will be asserted High. The INT will be held in the High state until the fault is removed, and the appropriate bit in the Status Register 0 is cleared by the CLINT0 command. This fault reporting technique is described in detail in the Logic Commands and Registers section.
Desaturation Detector
The Desaturation Detector is a comparator integrated into the output driver of each phase channel. It provides an additional means to protect against "Short-to-Ground" fault condition when the output node gets shorted to the supply voltage (short across the high-side FET).
Figure 13. Short to Ground Detection When switching from low-side to high-side, the high-side will be commanded ON after the end of the deadtime. The deadtime period starts when the low-side is commanded OFF. If the voltage at PX-HS_S is less than 1.4V below VBAT after the blanking time (tBLANK) a desaturation fault is initiated. An additional 1ms digital filter is applied from the initiation of the desaturation fault before it is registered, and all phase drivers are turned OFF (placed in a high impedance state). If the desaturation fault condition clears before the filter time expires, the fault is ignored and the filter timer resets. Valid faults are registered in the fault status register, which can be retrieved by way of the SPI. Additional SPI commands will mask the INT flag and disable output stage shutdown, due to desaturation and phase errors. See the Logic Commands and Registers section for details on masking INT behavior and disabling the protective function.
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FUNCTIONAL INTERNAL BLOCK DESCRIPTION INTRODUCTION
The Phase Error Flag is the triple OR of phase errors from each phase. Each phase error is the OR of the high side and low side phase errors. This flag can generate an interrupt if the appropriate mask bit is set. The INT will be held in the High state until the fault is removed, and the appropriate bit in the Status Register 0 is cleared by the CLINT1 command. This fault reporting mechanism is described in detail in the Logic Commands and Registers section.
HOLD OFF CIRCUIT
The IC guarantees the output FETs are turned off in the absence of VDD or VPWR by means of the Hold off circuit. A small current source, generated from VBAT, typically 100 A, is mirrored and pulls all the output gate drive pins low when VDD is less than about 3.0V, RST is active (low), or when VLS is lower than the VLS_Disable threshold.
CHARGE PUMP
The Charge Pump circuit provides the basic switching elements required to implement a charge pump when combined with external capacitors and diodes for enhanced low voltage operation. When the 33927 is connected per the typical application using the charge pump (see Figure 17), the regulation path for VLS includes the charge pump and a linear regulator. The regulation set point for the linear regulator is nominally at 15.34V. As long as VLS output voltage (VLSOUT) is greater than the VLS analog regulator threshold (VLSATH) minus VTHREG, the charge pump is not active. If VLSOUT < VLSATH - VTHREG the charge pump turns ON until VLSOUT > VLSATH - VTHREG + VHYST VHYST is approximately 200mV. VLSATH will not interfere with this cycle even when there is overlap in the thresholds due to the design of the regulator system. The maximum current the charge pump can supply is dependent on the pump capacitor value and quality, the pump frequency (nominally 130kHz) and the Rdson of the pump FETs. The effective charge voltage for the pump capacitor would be VBAT - 2*VDIODE. The total charge transfer would then be CPUMP * (VBAT - 2*VDIODE). Multiplying by the switch frequency gives the theoretical current the pump can transfer: FPUMP * CPUMP * (VBAT - 2*VDIODE). NOTE: There is also another smaller, fully integrated charge pump (Trickle Charge Pump - see Figure 2), which is used to maintain the high-side drivers' gate VGS in 100 percent duty cycle modes.
Figure 14. Short to Battery Detection Phase Comparator
Faults could also be detected as Phase Errors. A phase error is generated if the output signal (at Px_HS_S) does not properly reflect the drive conditions. A phase error is detected by a Phase Comparator. The Phase Comparator compares the voltage at the Px_HS_S node with a reference of one half the voltage at the VBAT pin. A high side phase error (which will also trigger the Desaturation Detector) occurs when the high side FET is commanded on, and Px_HS_S is still low at the end of the deadtime and blanking time duration. Similarly, a LS phase error occurs when the low side FET is commanded on, and the Px_HS_S is still high at the end of the deadtime and blanking time duration.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES RESET AND ENABLE
The 33927 has three power modes of operation described in Table 5. There are three global control inputs (RST, EN1, EN2), which together with the status of the VDD and VLS, control the behavior of the IC. The operating status of the IC can be described by the following three modes: Sleep Mode - When RST is low, the IC is in Sleep Mode. The current consumption of the IC is at minimum. * Standby Mode - The RST input is high while one of the Enable inputs is low. The IC is fully biased up and operating, all the external FETs are actively turned off by both high-side and low-side gate drives. The IC is ready to enter the Enable Mode. * Enable Mode - In order to enter the Enable Mode (normal mode of operation), and to operate the outputs, the RST input must be high, and both Enable inputs EN1 and EN2 must also be high.
Table 5. Functions of RST, EN1 and EN2 Pins
RST 0 EN1, EN2 xx Mode of Operation (Driver Condition) Sleep Mode - in this mode (low quiescent current) the driver output stage is switched-off with a weak pull-down. All error and SPI registers are cleared. The internal 5.0V regulator is turned off and VDD is pulled low. Logic outputs are clamped to GND. Standby Mode - IC fully biased up and all functions are operating, the output drivers actively turn off all of the external FETs. The SPI port is functional. Logic level outputs are driven with low impedance. VDD, Charge Pump and VLS regulators are all operating. The IC is ready to move to Enable Mode. Enable Mode - (normal operation). Drivers are enabled; output stages follow the input command. After Enable, outputs require a pulse on Px_LS before corresponding HS outputs will turn on in order to recharge bootstrap capacitor. All error pin and register bits are active if detected.
1
0x x0
1
11
* After entry to Enable Mode, the IC requires a pulse on Px_LS in order to charge the bootstrap capacitor before allowing the Px_HS to turn on. This pulse should be about 50 s to guarantee the bootstrap capacitor is charged, but the IC does not enforce this condition. If
there is an alternate means of pre-charging the bootstrap capacitor, i.e. an external resistor from Px_HS_S to GND, then a very brief pulse of 1.0 s is sufficient to reset the logic.
Table 6. Functional Ratings (TJ=-40C to 150C and supply voltage range VBAT = VPWR = 5.0V to 45V, C = 0.47F)
Characteristic Default State of input pin Px_LS, EN1, EN2, RST, SI, SCLK, if left open (Driver output is switched off, high impedance mode) Default State of input pin Px_HS, CS if left open (49) (Driver output is switched off, high impedance mode) Notes 49. To assure a defined status for all inputs, these pins are internally biased by pull-up/down current sources. High (>2.0V)
(49)
Value Low (<1.0V)
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS COMMAND DESCRIPTIONS
The IC contains internal registers to control the various operating parameters, modes, and interrupt characteristics. These commands are sent and status is read via 8-bit SPI commands. The IC will use the last eight bits in a SPI transfer, so devices can be daisy-chained. The first three bits in a SPI
Table 7. Command List
Command 000x xxxx 0010 xxxx 0011 xxxx 010x xxxx 0110 xxxx Name NULL MASK0 MASK1 Mode CLINT0 Description These commands are used to read IC status. These commands do not change any internal IC status. Returns Status Register 0-3, depending on sub command. Sets a portion of the interrupt mask using lower four bits of command. A "1" bit enables interrupt generation for that flag. INT remains asserted if uncleared faults are still present. Returns Status Register 0. Sets a portion of the interrupt mask using lower four bits of command. A "1" bit enables interrupt generation for that flag. INT remains asserted if uncleared faults are still present. Returns Status Register 0. Enables Desat/Phase Error Mode. Enables FULLON Mode. Locks further Mode changes. Returns Status Register 0. Clears a portion of the fault latch corresponding to MASK0 using lower four bits of command. A 1 bit clears the interrupt latch for that flag. INT remains asserted if other unmasked faults are still present. Returns Status Register 0. Clears a portion of the fault latch corresponding to MASK1 using lower four bits of command. A 1 bit clears the interrupt latch for that flag. INT remains asserted if other unmasked faults are still present. Returns Status Register 0. Set deadtime with calibration technique. Returns Status Register 0.
word can be considered to be the Command with the trailing five bits being the data. The SPI logic will generate a framing error and ignore the SPI message if the number of received bits is not eight or if it is not a multiple of eight. After RST, the first SPI result returned is Status Register 0.
0111 xxxx
CLINT1
100x xxxx
DEADTIME
FAULT REPORTING AND INTERRUPT GENERATION
Different fault conditions described in the previous chapters can generate an interrupt - INT pin output signal asserted high. When an interrupt occurs, the source can be read from Status Register 0, which is also the return word of most SPI messages. Faults are latched on occurrence, and the interrupt and faults are only cleared by sending the corresponding CLINTx command. A fault that still exists will continue to assert an interrupt. Note: If there are multiple pending interrupts, the INT line will not toggle when one of the faults is cleared. Interrupt processing circuitry on the host must be level sensitive to correctly detect multiple simultaneous interrupt. Thus, when an interrupt occurs, the host can query the IC by sending a NULL command; the return word contains flags
indicating any faults not cleared since the CLINTx command was last written (rising edge of CS) and the beginning of the current SPI command (falling edge of CS). The NULL command causes no changes to the state of any of the fault or mask bits. The logic clearing the fault latches occurs only when: 1. A valid command had been received(i.e. no framing error); 2. A state change did not occur during the SPI message (if the bit is being returned as a 0 and a fault change occurs during the middle of the SPI message, the latch will remain set). The latch is cleared on the trailing (rising) edge of the CS pulse. Note, to prevent missing any faults the CLINTx command should not generally clear any faults without being observed; i.e. it should only clear faults returned in the prior NULL response.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
NULL COMMANDS
This command is sent by sending binary 000x xxxx data. This can be used to read IC status in the SPI return word. Message 000x xx00 reads Status Register 0. Message 000x xx01 through 000x xx11 read additional internal registers.
Table 8. NULL Commands
SPI Data Bits Write Reset 7 0 6 0 5 0 4 x 3 x 2 x 1 0 0 0
NULL Commands are described in detail in the STATUS REGISTERS section of this document.
MASK Command
This is the mask for interrupts. A bit set to "1" enables the corresponding interrupt. Because of the number of MASK bits, this register is in two portions: 1. MASK0 2. MASK1 Both are accessed with 0010 xxxx and 0011 xxxx patterns respectively. Figure illustrates how interrupts are enabled and faults cleared. CLINT0 and CLINT1 have the same format as MASK0 and MASK1 respectively, but the action is to clear the interrupt latch and status register 0 bit corresponding to the lower nibble of the command.
Table 9. MASK0 Register
SPI Data Bits Write Reset 7 0 6 0 5 1 4 0 3 x 1 2 x 1 1 x 1 0 x 1
INTERRUPT HANDLING
To Status Register From MASKx:N Register MASK Bit
INT Source Various Faults INT Clear From Clint Command
S
Fault
net N INT
Latch R
net 0
Figure 15. Interrupt Handling Table 10. MASK1 Register
SPI Data Bits Write Reset 7 0 6 0 5 1 4 1 3 x 1 2 x 1 1 x 1 0 x 1
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 11. Setting Interrupt Masks
Mask:bit MASK0:0 MASK0:1 MASK0:2 MASK0:3 MASK1:0 Description Overtemperature on any gate drive output generates an interrupt if this bit is set. Desaturation event on any output generates an interrupt if this bit is set. VLS undervoltage generates an interrupt if this bit is set. Overcurrent Error-if the overcurrent comparator threshold is exceeded, an interrupt is generated. Phase Error-if any Phase comparator output is not at the expected value when an output is command on, an interrupt is generated. This signal is the XOR of the phase comparator output with the output drive state, and blacked for the duration of the desaturation blanking interval. In FULLON mode, this signal is blanked and cannot generate an error. MASK1:1 MASK1:2 MASK1:3 Framing Error-if a framing error occurs, an interrupt is generated. Write Error after locking. Reset Event-If the IC is set or disabled, an interrupt occurs. Since the IC will always start from a reset condition, this can be used to test the interrupt mechanism because when the IC comes out of RESET, an interrupt will immediately occur.
MODE COMMAND
This command is sent by sending binary 010x xxxx data.
Table 12. MODE Command
SPI Data Bits Write 7 0 6 1 5 0 4 0 3 Desaturation Fault Mode 0 2 0 1 FULLON Mode 0 0 Mode Lock 0
Reset
0
* Bit 0-Mode Lock is used to enable or disable Mode Lock. If Bit 0 is set, changes to the internal registers are disallowed to prevent inadvertent changes. This bit cannot be cleared once set. Since the mode Lock mode can only be set, this bit prevents any subsequent, and likely erroneous, mode, deadtime, or mask register changes from being received. The only way to clear this bit is to RESET the IC. If an attempt is made to write to a register when Mode Lock is enabled, a Write Error fault is generated. * Bit 1-FULLON Mode. If this bit is set, programmed deadtime control is disabled, making it is possible to have both highand low-side drivers in a phase on simultaneously. This could be useful in special applications such as alternator regulators, or switched-reluctance motor drive applications. There is no deadtime control in FULLON mode. Input signals directly control the output stages, synchronized with the internal clock. This bit is a "0", after RESET. Until overwritten, the IC operates normally; deadtime control and logic prevents both outputs from being turned on simultaneously. * Bit 3- Desaturation Fault Mode controls what happen when a desaturation event is detected. When set to "0", any desaturation on any channel causes all six output drivers to shutoff. The drivers can only be re-enabled by executing the CLINT command. When 1, desaturation faults are completely ignored. Bit 3 controls behavior if a Desaturation, or Phase Error event is detected. The possibilities are: -- 0: Default: When a Desaturation, or Phase Error event is detected on any channel, all channels turn off and generates an Interrupt, if interrupts are enabled. -- 1: Disable: Desaturation /Phase Error channel shutdown is disabled, but interrupts are still possible if unmasked.
Sending a MODE command and setting the Mode Lock simultaneously are allowed. This sets the requested mode and locks out any further changes.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
DEADTIME COMMAND
Deadtime prevents the turn-on of both transistors in the same phase until the deadtime has expired. The deadtime timer starts when a FET is commanded off (see Figure 6 and Figure 11). The deadtime control is disabled by enabling the FULLON mode. The deadtime is set by sending the DEADTIME command (100x xxx1), and then sending a calibration pulse of CS. This pulse must be 16 times longer than the required deadtime (see Figure 16). Deadtime is measured in cycle times of the internal time base, fTB. This measurement is divided by 16 and stored in an internal register to provide the reference for timing the deadtime between high and low gate transactions in the same phase. For example: the internal time base is running at 20MHz and a 1.5 s deadtime is required. First a DEADTIME command is sent (using the SPI), then a CS is sent. The CS pulse is 16*1.5=24 s wide. The IC measures this pulse as 24000ns/50ns = 480 clock cycles and stores 480/16=30 in the deadtime register. Until the next deadtime calibration is
Table 13. .DEADTIME Command
SPI Data Bits Write Reset 7 1 6 0 5 0 4 x
performed, 30 clock cycles will separate the turn off and turn on gate signals in the same phase. The worst case error immediately after calibration will be +0/-1 time base cycle, for this example +0ns/-50ns. Note that if the internal time base drifts, the effect on dead time will scale directly. Sending a ZERO DEADTIME command (100x xxx0) sets the deadtime timer to 0. However, simultaneous turn-on of high-side and low-side FETs in the same phase is still prevented unless the FULLON command has been transmitted. There is no calibration pulse expected after receiving the ZERO DEADTIME command. After RESET, deadtime is set to the maximum value of 255 time base cycles (typically 15 s). The IC ignores any SPI data that is sent during the calibration pulse. If there are any transitions on SI or SCLK while the Deadtime CS pulse is low, a Framing Error will be generated, however, the CS pulse will be used to calibrate the deadtime
3 x x
2 x x
1 x x
0 ZERO/ CALIBRATE x
Deadtime Calibration Pulse CS
SCLK
SI
DEADTIME Command
SO
Figure 16. Deadtime Calibration
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
STATUS REGISTERS
After any SPI command, the status of the IC is reported in the return value from the SPI port. There are four variants of the NULL command used to read various status in the IC.
Other commands return a general status word in the Status Register 0. There are four Status Registers in the IC. Status Register 0 is most commonly used for general status. Registers one through three are used to read or confirm internal IC settings.
Status Register 0 (Status Latch Bits)
This register is read by sending the NULL0 command (000x xx00). It is also returned after any other command. This command returns the following data:
Table 14. Status Register 0
SPI Data Bits Results Register 0 Read Reset 1 0 0 0 0 0 7 RESET Event 6 Write Error 5 Framing Error 4 Phase Error 3 Overcurrent 2 Low VLS 1 DESAT Detected on any Channel 0 0 TLIM Detected on any Channel 0
All status bits are latched. The latches are cleared only by sending a CLINT0 or CLINT1 command with the appropriate bits set. If the status is still present, that bit will not clear. CLINT0 and CLINT1 have the same format as MASK0 and MASK1 respectively. * Bit 0-is a flag for Overtemperature on any channel. This bit is the OR of the latched three internal TLIM detectors.This flag can generate an interrupt if the appropriate mask bit is set. * Bit 1-is a flag for Desaturation Detection on any channel. This bit is the OR of the latched three internal high-side desaturation detectors and phase error logic. Faults are also detected on the low-side as phase errors. A phase error is generated if the output signal (at Px_HS_S) does not properly reflect the drive conditions. The phase error is the triple OR of phase errors from each phase. Each phase error is the OR of the HS and LS phase errors. An HS phase error (which will also trigger the desaturation detector) occurs when the HS FET is commanded on, and the Px_HS_S is still low in the deadtime duration after it is driven ON. Similarly, a LS phase error occurs when the LS FET is commanded on, and the Px_HS_S is still high in the deadtime duration after the FET is driven ON. This flag can generate an interrupt if the appropriate mask bit is set. * Bit 2- is a flag for Low Supply Voltage. This bit is latched, thus a prior low voltage event is returned once before being cleared on read. This flag can generate an interrupt if the appropriate mask bit is set. * Bit 3-is a flag for the output of the Overcurrent Comparator. This flag can generate an interrupt if the appropriate mask bit is set. * Bit 4-is a flag for a Phase Error. If any Phase comparator output is not at the expected value when just one of the individual high- or low-side outputs is enabled, the fault flag is set. This signal is the XOR of the phase comparator output with the output driver state, and blanked for the duration of the desaturation blanking interval. This flag can generate an interrupt if the appropriate mask bit is set. * Bit 5-is a flag for a Framing Error. A framing error is a SPI message not a multiple of eight bits (a 0-length message is also a framing error), or SI, or SCLK toggling detected while measuring the Deadtime calibration pulse. This would typically be a transient or permanent hardware error, perhaps due to noise on the SPI lines. This flag can generate an interrupt if the appropriate mask bit is set. * Bit 6-indicates a Write Error After the Lock bit is set. A write error is any attempted write to the MASKn, Mode, or a Deadtime command after the Mode Lock bit is set. A write error is any attempt to write any other command than the one defined in the Table 7. This would typically be a software error. This flag can generate an interrupt if the appropriate mask bit is set. * Bit 7-is set upon exiting RST. It can be used to test the interrupt mechanism or to flag for a condition where the IC gets reset without the host being otherwise aware. This flag can generate an interrupt if the appropriate mask bit is set.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Status Register 1 (MODE Bits)
This register is read by sending the NULL1 command (000x xx01). This is guaranteed to not affect IC operation and returns the following data:
Table 15. Status Register 1
SPI Data Bits Results Register 1 Read Reset 0 0 7 0 6 Desaturation Mode 5 Zero Deadtime Set 0 4 Calibration Overflow 3 Deadtime Calibration 2 0 1 FULLON Mode 0 Lock Bit
0
0
0
0
0
* Bit 0-Lock Bit indicates the IC registers (Deadtime, MASKn, CLINTn, and Mode) are locked. Any subsequent write to these registers is ignored and will set the Write Error flag. * Bit 1- is the present status of FULLON Mode. If this bit is set to "0", the FULLON mode is not allowed. A "1" indicates the IC can operate in FULLON Mode (both High-Side and Low-Side FETs of one phase can be simultaneously turned on). * Bit 3-indicates Deadtime Calibration occurred. It will be "0" until a successful Deadtime command is executed. This includes the Zero Deadtime setting, as well as a Calibration Overflow. * Bit 4-is a flag for a Deadtime Calibration Overflow. * Bit 5-is set if Zero Deadtime is commanded. * Bit 6-reflects the current state of the Desaturation/Phase Error turn-off mode.
Status Register 2 (MASK bits)
This register is read by sending the NULL2 command (000x xx10). This is guaranteed to not affect IC operation and returns the following data:
Table 16. Status Register 2
SPI Data Bits Results Register 2 Read Reset 1 1 1 1 1 1 1 1 7 Mask1:3 6 Mask1:2 5 Mask1:1 4 Mask1:0 3 Mask0:3 2 Mask0:2 1 Mask0:1 0 Mask0:0
Status Register 3 (Deadtime)
This register is read by sending the NULL3 command (000x xx11). This is guaranteed to not affect IC operation and returns the following data:
Table 17. Status Register 3
SPI Data Bits Results Register 3 Read Reset 0 0 0 0 0 0 0 0 7 Dead7 6 Dead6 5 Dead5 4 Dead4 3 Dead3 2 Dead2 1 Dead1 0 Dead0
These bits represent the calibration applied to the internal oscillator to generate the requested deadtime. If calibration is not yet performed, all these bits return 0 even though the actual dead time is the maximum.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
IC Initialization
Here is a possible flow to initialize the IC and its software environment. 1. Apply power (VBAT) to module 1.1. This doesn't wake-up the IC because VPUMP isn't powered. VBAT current will be low because it will only be leakage and the small hold off bias current. 2. Power-up VPUMP 2.1. No changes will occur until RST rises 3. Remove RST (EN1 and EN2 are still low) 3.1. As the module powers up, RST will rise, allowing the IC to power-up. The charge pump will start, and VPWR and VLS will stabilize. 3.2. VDD will rise as the internal regulator charges the external reservoir capacitor and the IC will come out of reset. 3.3. Initialize interrupt handler for MCU 3.4. Interrupt will occur because of the RESET (Interrupt processing will occur here) 4. Initialize registers 4.1. Initialize MASK register by sending 0010 xxxx or 0011 xxxx to mask out unwanted interrupts. 4.2. Send MODE command with desired bits, and also the Lock bit. e.g. 01000001. This prevents further mode changes. 5. Bring EN1 & EN2 high 5.1. This fully enables the IC
MAIN LOOP 1. While (forever) 1.1. Send SPI messages (except NULL1-3), read results 1.2. If sending NULL1-3 messages, use a semaphore to detect interrupts 1.2.1. Set Semaphore flag in RAM 1.2.2. Send NULL1-3 1.2.3. Send NULL0, read SR1-3 1.2.4. If Semaphore is still set, then result is good, else go to 1.2.1 (because an interrupt has gotten in the way) 1.2.5. Clear semaphore 2. END Interrupt Handler
When an interrupt occurs, the general procedure is to send NULL0 and NULL1 commands to determine what happened, take corrective action (if needed), clear the fault and return. Because the return value from a SPI command is actually returned in the subsequent message, main-loop software that tries to read SR1, SR2 or SR3, may experience an interrupt between sending the SPI command and the subsequent read. Thus if these registers are to be read, special care must be taken in the software to ensure that the correct results are being interpreted. 1. Interrupt Service Routine: 1.1. Disable further interrupts from 33927 1.2. Clear semaphore in 1.2.1 of Main loop. This indicates to the main loop that an interrupt occurred and that the return value it gets may not be as expected. 1.3. Send NULL0 Command. Ignore return value, since this will have been associated with some unknown previous command 1.4. Send NULL0 Command. The return value will be SR0 from the previous NULL0 command 2. Process Bits in SR0 and correct any faults 3. Send CLINT0 command to clear known (i.e. processed faults from SR0) faults 0:3 4. Send CLINT1 command to clear processed faults 4:7. Note, the return SR0 register from this command is actually read in the main routine. 5. Re-enable interrupts from the 33927 6. Return
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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES
PROTECTION AND DIAGNOSIS FEATURES
Table 18. 33927 Fault Protection
No. 1 Fault Phase Output Shorted to VBAT (High-Side FET Shorted) Cause Wire harness shorted to battery Detection 33927 Protective Action
* Directly sensed by ADC as voltage across RSENSE * Overcurrent Comparator output Drain-to-Source short on the OC_OUT monitoring High-Side FET (Overcurrent Error) * Low-Side Phase Error * Direct PHASEx output monitoring
Wire harness shorted to battery
* * * *
All external FETs turned off Fault bit set in Status Register INT pin set high OC_OUT pin set high
2
Phase Output Shorted to Ground (RSENSE Bypassed) Low-Side FET Shorted
* Desaturation Error * High-Side Phase Error * Direct PHASEx output monitoring
* All external FETs turned off * Fault bit set in Status Register * INT pin set high
3
Drain-to-Source short on the * Directly sensed by the ADC as voltage across RSENSE Low-Side FET
* Overcurrent Comparator output OC_OUT high (Overcurrent error) * Desaturation Error * High-Side Phase Error * Direct PHASEx output monitoring
4 High-Side FET Opened Module board assembly issue
* * * *
All external FETs turned off Fault bit set in Status Register INT pin set high OC_OUT pin set high
* Desaturation Error * High-Side Phase Error * Directly sensed by ADC as voltage across RSENSE * Low-Side Phase Error * Directly sensed by ADC as voltage across RSENSE
* All external FETs turned off * Fault bit set in Status Register * INT pin set high * All external FETs turned off * Fault bit set in Status Register * INT pin set high
5
Low-Side FET Opened
Module board assembly issue
6
Phase Output Opened (No Load)
Wire harness open
NOTE: Other protective actions should be taken at the system level by the controlling microcontroller or DSP. It is possible to disable all automatic shutdowns except for VLS undervoltage. Even when masked, faults will be registered by the status registers.
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TYPICAL APPLICATIONS PROTECTION AND DIAGNOSIS FEATURES
TYPICAL APPLICATIONS
VBAT +12V Nom.
+
To Other Two Phases
PUMP
VPWR
VBAT
VPUMP PGND MAIN CHARGE PUMP TRICKLE CHARGE PUMP 5V REG. VDD OSCILLATOR VLS REG. VLS VDD UV DETECT
3X
HOLD -OFF CIRCUIT
RST INT EN1 EN2 PX_HS PX_LS CS SI SCLK SO
3 3 3
PX_BOOT T-LIM VBAT HIGHSIDE DRIVER PX_HS_G
Cx_Boot Rg_HS (Optional) Phase x Output To Motor
CONTROL LOGIC
+ DESAT. 1.4V COMP + -
PX_HS_S
+ PHASE VBAT COMP. LOWSIDE DRIVER + I-SENSE AMP. AMP_OUT AMP_N AMP_P VLS_CAP
PX_LS_G
Rg_LS (Optional)
PHASEX OC_OUT GND(2) + OVER-CUR. COMP. VSS OC_TH
PGNDX
Phase Return
RSense
To ADC
Figure 17. Typical Application Diagram Using Charge Pump (+12V Battery System)
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TYPICAL APPLICATIONS PROTECTION AND DIAGNOSIS FEATURES
VBAT
+42V Nom.
+
+14V Nom.
To Other Two Phases
PUMP
VPWR
VBAT
VPUMP PGND MAIN CHARGE PUMP TRICKLE CHARGE PUMP 5V REG. VDD OSCILLATOR VLS REG. VLS VDD UV DETECT
3X
HOLD -OFF CIRCUIT
RST INT EN1 EN2 PX_HS PX_LS CS SI SCLK SO
3 3 3
PX_BOOT T-LIM VBAT HIGHSIDE DRIVER PX_HS_G
Cx_Boot Rg_HS (Optional) Phase x Output To Motor
CONTROL LOGIC
+ DESAT. 1.4V COMP + -
PX_HS_S
+ PHASE VBAT COMP. LOWSIDE DRIVER + I-SENSE AMP. AMP_OUT AMP_N AMP_P VLS_CAP
PX_LS_G
Rg_LS (Optional)
PHASEX OC_OUT GND(2) + OVER-CUR. COMP. VSS OC_TH
PGNDX
Phase Return
RSense
To ADC
Figure 18. High-Voltage Application Diagram (+42V Battery System)
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Figure 19. Power Dissipation Profile of Application Using Charge Pump Reference application with: * Pump capacitor: 1F MLC * Pump filter capacitor: 47F low ESR aluminum electrolytic * Pump diodes: MUR120 * Output FET gate charge: 240 nC @ 10V * PWM Frequency: 20kHz * Switching Single Phase Below approximately 17V the charge pump is actively regulating Vpwr. The increased power dissipation is due to the charge pump losses. Above this voltage the charge pump oscillator shuts down and Vbat is passed through the pump diodes directly to Vpwr.
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PROTECTION AND DIAGNOSIS FEATURES
Figure 20. Power Dissipation Profile of Application Not Using Charge Pump Reference application with: * Output FET gate charge: 240 nC @ 10V * PWM Frequency: 20kHz * Switching Single Phase * No connections to PUMP or VPUMP * VPWR connected to Vbat If VPWR is supplied by a separate pre-regulator, the power dissipation profile will be nearly flat at the value of the pre-regulator voltage for all Vbat voltages.
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGING DIMENSION
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PACKAGING PACKAGING DIMENSION (CONTINUED)
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REVISION HISTORY
REVISION HISTORY
REVISION 2.0
DATE 8/2007
DESCRIPTION OF CHANGES * Initial Release
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MC33927 Rev. 2.0 8/2007

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